Dynamic random access memory (DRAM) and static random access memory (SRAM) are two kinds of random access memory devices. Each RAM device consists of an array or several arrays of memory cells. In general, each memory cell stores a data value which has a logic "1" value or a logic "0" value. Memory devices using RAM cells are compact in size and low in cost, and are widely used in electronic systems such as computers.
The reliability of each of the memory cells determines the reliability of the system. The failure of one memory cell in a multi-cell memory device can result in malfunctioning of the entire system that employs the memory device. Therefore, it is important that all memory cells in a memory device function properly.
FIG. 1 is a schematic diagram of a conventional SRAM cell 100. SRAM Cell 100 includes cross-coupled N-channel pulldown transistors 101 and 102, N-channel access transistors 103 and 104, and load resistors 105 and 106. Memory cell 100 is coupled to word line 110, data bit line BIT, and complementary bit line BIT. Data bit line BIT BIT and complementary bit line form a bit line pair.
SRAM Cell 100 stores a data value which can be identified by the voltages at nodes 121 and 122. When one of nodes 121 and 122 is pulled up to a logic high voltage, the other one of nodes 121 and 122 is pulled down to a logic low voltage. Thus, e.g., a logic high voltage at node 121 and a logic low voltage at node 122 can represent a logic "1" data value.
A "write-disturb mode" is a condition where the voltages across an access transistor, such as the voltages at node 121 and node 123, are different. A write disturb mode often occurs when SRAM cell 100 stores a data value, word line 110 is deselected, and an opposite data value is written into a second SRAM cell (not shown) which shares bit lines BIT and BIT with SRAM cell 100. Thus if a logic value "1" is stored in SRAM cell 100, a write-disturb mode is created if a logic value "0" is written into the second SRAM cell.
In this condition, the voltage difference between bit line BIT and node 121 is sufficient to cause sub-threshold leakage current to flow between node 121 and bit line BIT through access transistor 103. The amount of sub-threshold leakage current which flows through transistor 103 depends on the integrity of transistor 103. A faulty transistor 103 results in a stronger leakage current between node 121 and bit line BIT. If this leakage current exceeds a certain level, the data value that is stored in SRAM cell 100 can be corrupted.
A long-write test identifies cells that exhibit an excessive leakage current in the presence of a write disturb condition such that the stored data are corrupted. A specific faulty memory cell can be identified with a long-write test. There are three steps in a long-write test. First, a known data value is written into the cells to be tested and the word lines are deselected. Second, an opposite data value is written into a cell on the same column as the cells to be tested over a long period of time to create a write-disturb mode. The "long period" is defined relative to the time required for a regular write access of the cell. A long period is normally a few microseconds in duration. Third, the tested cells are read to determine whether or not the data value stored therein has been corrupted.
Memory failure during a write-disturb is also a problem for DRAM cell arrays. FIG. 2A is a schematic diagram of a DRAM cell 200. Memory cell 200 includes access transistor 201 and storage capacitor 207. Word line 203 is coupled to the gate of access transistor 201, while bit line 205 is coupled to the source of transistor 201. DRAM cell 200 stores a data value which can be identified by the voltage at node 208. A defective access transistor 201 may cause leakage between its drain and its source, thereby causing the stored data value to be corrupted when another cell is accessed.
FIG. 2B is a schematic diagram of a dual port DRAM cell. Write transistor 211 is coupled between storage capacitor 217 and write bit line 215. The gate of write transistor 211 is coupled to write word line 216. Read transistor 212 is coupled across read word line 213 and read bit line 219. The gate of read transistor 212 is coupled to storage capacitor 217. In this configuration, a defective write transistor 211 may cause a drain-to-source leakage strong enough to disrupt the stored data value. Similarly, a defective read transistor 212 may cause a strong gate-to-drain or gate-to-source leakage to disrupt the stored data value at capacitor 217. Thus, for both the single port or multi-port DRAM cell arrays, a long-write test of the array is similarly required.
Among all memory failures, over 90% occur during write-disturb mode. Thus, it is essential that each memory device be thoroughly tested for long-write failures. FIG. 3 is a schematic diagram of a conventional SRAM device 300. SRAM device 300 shown in FIG. 3 has three word blocks, block 1, block 2, and block 3. Each word block consists of four columns, or bits, with each bit having a pair of bit lines. For example, block 1 has bit line pairs 160, 161, 162, and 163. The SRAM device is also divided into several rows, such as rows 141-150. Within a word block, memory cells in each row represent a word. For example, in word block 1, on row 141, the four cells connected to bit lines 160-163 represent one word.
Design constraints dictate that memory cells in DRAM device 300 can be accessed one word at a time. This means that a long write test on a memory cell array is normally performed on the cells word by word.
As an example, a long-write test on SRAM device 300 will begin with word block 1. A known data value, e. g., a logic "1", is provided from data bus 572 and is written into each of the cells in block 1, from row 141 to row 150. The word lines of rows 141-150 are then deselected. An opposite data value, e.g., a logic "0", is provided by data bus 572 to the bit line pairs 160-163 of word block 1 to create a write-disturb mode. The data values stored in the memory cells of word block 1 are then read to determine if a data corruption has occurred. If word block 1 sustains the long-write test, word block 2 will be tested, and a similar process is used. The memory device is considered satisfactory if each cell in each word block sustains the test. This word by word, block by block test process of the prior art is time consuming.
In order to perform a long write test more efficiently, Devanney (U.S. Pat. No. 5,440,524) proposed the use of multiple column select circuits. The method proposed by Devanney would require extra circuitry outside of the memory cell array, making the layout design of the memory device complicated.